1. Field of the Invention
The embodiments of the invention generally relate to metal oxide semiconductor field effect transistors (MOSFETS) and, more particularly, to a strained MOSFET with carbon-doped source/drain regions and a method of forming the MOSFET.
2. Description of the Related Art
Current flowing through an electric field in the channel region of a field effect transistors is proportional to the mobility of the carriers (e.g., electrons in n-type field effect transistors (n-FETs) and holes in p-type field effect transistors (p-FETs) in that channel region. Different strains on the channel region can effect carrier mobility and, thus, current flow. For example, compressive stress on a channel region of a p-FET can enhance hole mobility. Contrarily, tensile stress on a channel region of an n-FET can enhance electron mobility. Various stress engineering techniques are known for imparting the desired stress on n-FET and p-FET channel regions. For example, as discussed in U.S. Pat. No. 6,885,084 of Murthy et al. issued on Apr. 26, 2005 and incorporated herein by reference, a compressive stress (i.e., a uni-axial compressive strain parallel to the direction of the current) can be created in the channel region of a p-FET by forming the source/drain regions with an alloy of silicon and germanium and a tensile stress (i.e., a uni-axial tensile strain parallel to the direction of the current) may be created in the channel region of an n-FET by forming the source/drain regions with an alloy of silicon and carbon.
One method of forming tensile stressor source/drain regions for n-FET performance enhancement is to amorphize source/drain regions with a carbon implant followed by re-crystallization of the implanted, amorphized source/drain regions. To maximize the stress effect of the re-crystallized silicon carbon source/drain regions, the carbon implant must be deep. Unfortunately, the deep carbon implant is limited because of the risk of simultaneously implanting carbon ions into the gate electrode and damaging the gate dielectric layer. Thus, there is a need in the art for an improved n-FET structure that provides optimum tensile stress to the channel region.